1. Field of the Invention
The present invention relates generally to increasing bus bandwidth in a computer system bus through posting input/output writes. Specifically, the present invention involves an apparatus and method of inhibiting interrupts during posted write transfers in a computer system.
2. Description of the Related Art
Many of the operations performed by a central processing unit ("CPU") are memory accesses on the system and input/output ("I/O") busses. Memory devices on the system bus respond quickly, allowing the CPU to operate at or near its maximum sustainable speed. I/O devices typically exhibit slower response times because they are usually accessed through a separate bus which is sometimes slower than the system bus and which utilizes a bus interface between the I/O bus and the system bus. In general, the CPU cannot terminate an I/O write cycle until the data has reached the intended destination and the system bus receives acknowledgment of this. The delay caused by I/O write operations is compounded in a multi-processor system because the bus interface or "bridge" may be placed between the System and I/O busses to arbitrate multiple processor transactions with devices on the I/O bus.
One conventional technique to allow a CPU to continue processing without waiting for the data for an I/O write cycle to reach its final destination is to "post" I/O write operations in the interface between the system bus and the I/O bus. (This interface is often called a bus bridge.) This simply means that the I/O bus bridge responds to the I/O write from the CPU immediately and "posts" the data in a buffer in the bus bridge. The data then propagates through the buffer and is delivered to the intended destination on the I/O bus. Posting permits the CPU write cycle to terminate on the system bus without waiting for the cycle to complete on the I/O bus.
In certain circumstances, conventional posted write techniques alleviate the I/O write delay; however, posting all write operations can lead to erroneous operation. For instance, when the CPU writes a control word (or mask) to the interrupt controller on the I/O bus to disable a specific interrupt or interrupts, the CPU no longer expects to receive the masked interrupt or interrupts. If the interrupt mask write operation is "posted" in the I/O bus bridge, the processor proceeds under the assumption that the masked interrupts will be inhibited. However, since the write cycle has not completed on the I/O bus (it is merely posted on the bus bridge), the interrupt controller has not received the mask. Thus, the interrupt controller may issue an unexpected interrupt and erroneous operations may result.
Conventionally, one of two approaches have been used to solve the potential inappropriate interrupt problem. The first approach is to refrain from posting those writes which can affect interrupts. During this time, all transactions on the system bus are delayed until the write affecting interrupts is completed. This approach is undesirable because it causes significant delay on the system bus until the I/O bus completes the write cycle.
The second approach involves the use of split transaction buses. This solution imposes a wait only on the processor originating the transaction, while freeing the multiprocessor ("MP") bus for use by other processors. The originating CPU waits until the bus bridge "reconnects" to the originating CPU and sends a signal indicating completion of the write cycle. Even though the system bus is released to permit other transactions to occur, the originating CPU still waits for the write cycle to complete. Although this approach is the less disruptive than holding the entire system bus in a wait state, a split transaction bus still requires the originating processor to wait until the write cycle completes.